Nonvolatile memory manufacturers such as manufacturers of NAND flash memory devices typically specify a maximum number of erase suspend operations for devices that allow for erase suspend operations. Exceeding the number of erase suspend operations specified in the operating specification can lead to either a higher raw Bit Error Rate (BER) or a bad block condition. Erase suspend means suspension of an erase command prior to completion of the erasure.
For some 1× nanometer TLC NAND devices the maximum number of erase suspends is only 10, or in some cases may be less than 10. This low number of allowed erase suspends is not sufficient to obtain desired quality of service levels.
Accordingly, there is a need for a method and apparatus that allows for increasing the number of erase suspend operations and that does not increase the BER or cause a bad block condition as a result of erase suspend operations.